For well over three decades, semiconductor memories such as DRAM's, SRAM's, ROM's, EPROM's, EEPROM's, Flash EEPROM's, Ferroelectric RAM's, MAGRAM's and others, have played a vital role in many electronic systems. Their functions for data storage, code (instruction) storage, and data retrieval/access (Read/Write) continue to span a wide variety of applications. Usage of these memories in both stand alone/discrete memory product forms, as well as embedded forms such as, for example, memory integrated with other functions like logic, in a module or monolithic IC, continues to grow. Cost, operating power, bandwidth, latency, ease of use, the ability to support broad applications (balanced vs. imbalanced accesses), and nonvolatility are all desirable attributes in a wide range of applications.
Soft error correction is a challenge facing digital memory designers as memory cells density within digital memory designs, in particular DRAM and SRAM designs, continues to increase. As density increases, a single random event such as alpha particle collision, is more likely to cause soft errors or bit flips. Also, as density increases, such events are more likely to result in a larger number of flipped bits versus lower density memory devices. As a result, soft error correction is of increasing concern and chip designers take care to choose semiconductor and packaging materials to minimize the occurrence of cell or bit upset events. However, in most systems, soft errors are inevitable and must be corrected for.
Typically, error correction schemes are employed to detect and correct for soft errors. For example, forward error correction may be used; such schemes store redundant data in each data word. Alternatively, roll-back error correction may be used; such schemes use error correction codes, such as parity or Hamming codes, to detect and correct bit errors. Typical implementations utilize single bit error correction/single bit error detection schemes. Also, error correction schemes capable of correcting additional bit errors are also known. During a typical Read Modify Write (RMW) cycle, a data word is read from memory and an error correction engine detects any bit errors. Then, assuming an error is detected, the entire data word, including corrected bit(s), is written back to the memory device. The access operations required to do so, including precharging the bit lines, results in delay and consumes power. In some systems, a data word may be distributedly stored across multiple memory devices. In these systems, the entire corrected word is written back, even though there may only be a single bit error corresponding to a single memory cell in only one of the memory devices resulting in increased latency and power consumption across all memory devices.